A novel damage-free high-k etch technique using neutral beam-assisted atomic layer etching (NBALE) for sub-32nm technology node low power metal gate/high-k dielectric CMOSFETs

Author

Min, K.S. ; Kang, C.Y. ; Park, C. ; Park, C.S. ; Park, B.J. ; Park, J.B. ; Hussain, M.M. ; Lee, Jack C. ; Lee, B.H. ; Kirsch, P. ; Tseng, H.-H. ; Jammy, R. ; Yeom, G.Y.

Author_Institution

SEMATECH, Austin, TX, USA

fYear

2009

Firstpage

1

Lastpage

4

Abstract

For the first time, a novel damage-free neutral beam-assisted atomic etching process has successfully demonstrated the removal of the residual high-k dielectric layer after gate patterning. Due to its neutralized atomic flux and chemical reaction, high etch selectivity is observed to improve device performance and reliability. This process should significantly enhance high-k/metal gate manufacturability.

Keywords

CMOS integrated circuits; MOSFET; plasma beam injection heating; sputter etching; chemical reaction; damage free high-k etch technique; gate patterning; low power metal gate-high-k dielectric CMOSFET; neutral beam assisted atomic layer etching; neutralized atomic flux; Atomic beams; Atomic layer deposition; CMOS technology; CMOSFETs; Dry etching; High K dielectric materials; High-K gate dielectrics; Materials science and technology; Particle beams; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424330

Filename

5424330