• DocumentCode
    1652677
  • Title

    Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

  • Author

    Chen, D.Y. ; Chiou, W.C. ; Chen, M.F. ; Wang, T.D. ; Ching, K.M. ; Tu, H.J. ; Wu, W.J. ; Yu, C.L. ; Yang, K.F. ; Chang, H.B. ; Tseng, M.H. ; Hsiao, C.W. ; Lu, Y.J. ; Hu, H.P. ; Lin, Y.C. ; Hsu, C.S. ; Shue, Winston S. ; Yu, C.H.

  • Author_Institution
    Integrated Interconnect & Packaging Div., Taiwan Semicond. Manuf. Co. Ltd., Hsin-Chu, Taiwan
  • fYear
    2009
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of bulk CMOS devices with and without e-SiGe/CESL stressors has been minimized. The presence of TSV caused no significant changes in Cu/ELK reliability. These excellent characteristics suggest the 300 mm 3D-IC processes are promising and suitable for adoption in next generation integrated circuits and interconnects.
  • Keywords
    CMOS integrated circuits; Ge-Si alloys; copper; foundries; integrated circuit interconnections; integrated circuit reliability; internal stresses; microassembling; three-dimensional integrated circuits; wafer bonding; wafer-scale integration; 3D die-to-wafer integration scheme; 3D-IC foundry technology; CMOS; Cu; SiGe; TSV formation; TSV wafer; bulk CMOS devices; device threshold voltage; die-to-wafer assembly; extreme thinning; high throughput die-to-wafer stacking; interconnects; leakage currents; next generation integrated circuits; size 28 nm; size 300 mm; through-silicon-via integration; Assembly; CMOS technology; Foundries; Integrated circuit reliability; Leakage current; Stacking; Three-dimensional integrated circuits; Threshold voltage; Through-silicon vias; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2009 IEEE International
  • Conference_Location
    Baltimore, MD
  • Print_ISBN
    978-1-4244-5639-0
  • Electronic_ISBN
    978-1-4244-5640-6
  • Type

    conf

  • DOI
    10.1109/IEDM.2009.5424350
  • Filename
    5424350