A generic tool-set for SoC multiprocessor debugging and synchronization

Current and future SoC designs will contain an increasing number of programmable units. To be able to tailor and debug these processors in their system context at the highest possible overall simulation speed, we propose a methodology and the necessary tooling for a multiprocessor debugging environment which allows a flexible runtime tradeoff between observability and simulation speed. This approach has been applied on a complex SoC case study.