• DocumentCode
    1653097
  • Title

    Design on power-rail esd clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process

  • Author

    Ker, Ming-Dou ; Chen, Wen-Yi ; Hsu, Kuo-Chun

  • Author_Institution
    Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2005
  • Firstpage
    606
  • Lastpage
    607
  • Keywords
    CMOS integrated circuits; MIS devices; electrostatic discharge; integrated circuit design; integrated circuit reliability; semiconductor device reliability; 1 V; 130 nm; 2.5 V; 3.3 V; CMOS process; ESD detection circuit; IC product reliability; electrostatic discharge; gate-oxide reliability; pMOS devices; power-rail ESD clamp circuit design; stacked nMOS devices; CMOS process; CMOS technology; Circuits; Clamps; Electrostatic discharge; Laboratories; Nanoelectronics; Power system protection; Threshold voltage; Variable structure systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International
  • Print_ISBN
    0-7803-8803-8
  • Type

    conf

  • DOI
    10.1109/RELPHY.2005.1493165
  • Filename
    1493165
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1653097