A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure

Author

Liao, Ta-Chuan ; Chen, Sheng-Kai ; Yu, Ming H. ; Wu, Chun-Yu ; Kang, Tsung-Kuei ; Chien, Feng-Tso ; Liu, Yen-Ting ; Lin, Chia-Min ; Cheng, Huang-Chung

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2009

Firstpage

1

Lastpage

4

Abstract

A novel gate-all-around low-temperature poly-Si (LTPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.

Keywords

random-access storage; silicon compounds; thin film transistors; LTPS-TFT; SONOS nonvolatile memory; SiO₂-SiN-SiO₂; charge-trapping memory device; field-enhanced carrier tunneling; field-enhanced nanowire structure; low-temperature poly-Si thin-film transistor; sidewall spacer formation; system-on-panel; Displays; Laser sintering; Lithography; Nanoscale devices; Nanostructures; Nonvolatile memory; SONOS devices; Strips; Thin film transistors; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424387

Filename

5424387