• DocumentCode
    1653773
  • Title

    Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC

  • Author

    Xu, Yuanzhe ; Yu, Wenjian ; Chen, Quan ; Jiang, Lijun ; Wong, Ngai

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Univ. of Hong Kong, Hong Kong, China
  • fYear
    2012
  • Firstpage
    1409
  • Lastpage
    1412
  • Abstract
    In this paper, we present a variational electromagnetic-semiconductor coupled solver to assess the impacts of process variations on the 3D integrated circuit (3D IC) on-chip structures. The solver employs the finite volume method (FVM) to handle a system of equation considering both the full-wave electromagnetic effects and semiconductor effects. With a smart geometrical variation model for the FVM discretization, the solver is able to handle both small-size or large-size variations. Moreover, a weighted principle factor analysis (wPFA) technique is presented to reduce the random variables in both electromagnetic and semiconductor regions, and the spectral stochastic collocation method (SSCM) is used to generate the quadratic statistical model. Numerical results validate the accuracy and efficiency of this solver in dealing with process variations in hybrid material through-silicon via (TSV) structures.
  • Keywords
    finite volume methods; integrated circuit modelling; stochastic processes; three-dimensional integrated circuits; 3D IC; 3D integrated circuit; FVM discretization; TSV structures; efficient variation-aware EM-semiconductor coupled solver; finite volume method; full-wave electromagnetic effects; hybrid material through-silicon via structures; on-chip structures; quadratic statistical model; semiconductor effects; smart geometrical variation model; spectral stochastic collocation method; variational electromagnetic-semiconductor coupled solver; wPFA technique; weighted principle factor analysis technique; Equations; Mathematical model; Rough surfaces; Solid modeling; Surface roughness; Three dimensional displays; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4577-2145-8
  • Type

    conf

  • DOI
    10.1109/DATE.2012.6176583
  • Filename
    6176583