A novel N-th order IIR switched-capacitor decimator building block with optimum implementation

Author

Martins, R.P. ; Franca, J.E.

Author_Institution

Inst. Superior Tecnico, Lisbon, Portugal

fYear

1989

Firstpage

1471

Abstract

A novel N-th order infinite-impulse response (IIR) switched-capacitor (SC) decimator building block with optimum implementation has been developed for realizing arbitrary baseband and antialiasing amplitude responses using a minimum number of switching waveforms and operational amplifiers with relaxed speed requirements. Alternative topologies can be adopted, depending on the acceptable capacitance spread and total capacitor area in the circuit as well as the performance under nonideal characteristics of the amplifiers. Practical designs of third-order and fourth-order IIR SC decimator building blocks with different factors of sampling rate reduction are presented for illustration purposes

Keywords

active networks; network topology; switched capacitor networks; transfer functions; IIR switched-capacitor decimator; N-th order; SC decimator building blocks; Z-transfer function; antialiasing amplitude responses; baseband amplitude responses; fourth-order; infinite-impulse response; operational amplifiers; optimum implementation; relaxed speed requirements; sampling rate reduction; third-order; topologies; Baseband; Capacitance; Circuit topology; Filtering; Finite impulse response filter; IIR filters; Operational amplifiers; Polynomials; Sampling methods; Switched capacitor circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100635

Filename

100635