• DocumentCode
    1655147
  • Title

    Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values

  • Author

    Kajihara, Seiji ; Saluja, Kewal K. ; Reddy, Sudhakar M.

  • Author_Institution
    Kyushu Institute of Technology
  • fYear
    2004
  • Firstpage
    108
  • Lastpage
    113
  • Keywords
    Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Electrons; Fault detection; Logic circuits; Logic testing; Sufficient conditions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2004. ETS 2004. Proceedings. Ninth IEEE European
  • Print_ISBN
    0-7695-2119-3
  • Type

    conf

  • DOI
    10.1109/ETSYM.2004.1347620
  • Filename
    1347620
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1655147