A novel on-chip electrostatic discharge (ESD) protection for beyond 500 MHz DRAM

Author

Narita, Kaoru ; Horiguchi, Yoko ; Fujii, Takeo ; Nakamura, Kunio

Author_Institution

LSI Memory Div., NEC Corp., Sagamihara, Japan

fYear

1995

Firstpage

539

Lastpage

542

Abstract

An on-chip electrostatic discharge (ESD) protection for high speed DRAMs that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the I/O transistor dimension, which acted also as a protection device in the conventional device. As a result, the ESD tolerance of 4 kV for the charged device model (CDM) test, 4 kV for the human body model (HBM) test, and 700 V for the machine model (MM) test were obtained. In addition, a DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure

Keywords

CMOS memory circuits; DRAM chips; capacitance; electrostatic discharge; large scale integration; protection; 500 to 660 MHz; 700 V to 4 kV; CMOS LSI; I/O capacitance; charged device model test; common discharge line; dynamic RAM; electrostatic discharge protection; high speed DRAMs; human body model test; machine model test; onchip ESD protection; Biological system modeling; Capacitance; Circuit testing; Electrostatic discharge; Humans; Minimization; Protection; Random access memory; Temperature; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499256

Filename

499256