An improved phase clock generator for interleaved and double-sampled switched-capacitor circuits

A simple, yet effective, approach to the generation of switches´ control signals to reduce timing-skew problems in interleaved and double-sampled switched-capacitor circuits is proposed. The new approach, unlike similar methods previously proposed, avoids the introduction of additional switches in the switched-capacitor circuits, at the cost of a minor increase of complexity in the clock phase generation. This has two main advantages. First, the performance degradation due to the additional switch is avoided. Second, it becomes extremely easy to build interleaved architectures combining preexisting analog blocks