• DocumentCode
    1657019
  • Title

    Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation

  • Author

    Vatajelu, Elena I. ; Figueras, Joan

  • Author_Institution
    Dept. of Electron. Eng., Univ. Politec. de Catalunya (UPC), Barcelona, Spain
  • fYear
    2012
  • Firstpage
    1343
  • Lastpage
    1348
  • Abstract
    The efficiency of different assist techniques for SRAM cell functionality improvement under the influence of random process variation is studied in this paper. The sensitivity of an SRAM cell functionality metrics when using control voltage level assist techniques is analyzed in read and write operation modes. The efficiency of the assist techniques is estimated by means of parametric analysis. The purpose is to find the degree of functionality metric improvement in each operation mode. The Acceptance Region concept is used for parametric analysis of SRAM cell functionality under random threshold voltage variations. In order to increase the reliability of the SRAM several assist techniques, chosen among the most efficient ones for each operation mode, are considered. This analysis offers a qualitative indication of the cell´s functionality improvement by means of the efficient computation of a metric in parameter domain analysis. The results are proven to have high correlation with the ones obtained by means of the classical Monte Carlo simulations with significant savings in comparing different assist techniques.
  • Keywords
    Monte Carlo methods; SRAM chips; failure analysis; integrated circuit reliability; SRAM cell functionality improvement; SRAM operation reliability; acceptance region concept; classical Monte Carlo simulations; control voltage level assist techniques; functionality metric improvement; parameter domain analysis; parametric analysis; parametric failure mitigation techniques; random process variation; random-threshold voltage variations; read-write operation modes; Computer architecture; Measurement; Microprocessors; Random access memory; Reliability; Support vector machines; Voltage control; SRAM Cell; Spec Violation Metric; Voltage Level Assist Techniques;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4577-2145-8
  • Type

    conf

  • DOI
    10.1109/DATE.2012.6176700
  • Filename
    6176700