Interconnect impact on the performance of a SET-based Network-on-Chip memory circuit

Generally, the memory module of a processor core occupies the most part of its area. In this sense, the power dissipation of that high density device module is an important issue for developing an integrated circuit, especially when considering the effects of dissipation due to interconnects. Nanoelectronic devices appear like an option for designing large integrated circuits, because of their lower power consumption compared to nowadays technologies. Among these nanoelectronic devices, single-electron transistors (SET) are known for their reduced area and power consumption features, which are orders of magnitude lower than CMOS devices. Taking that into account, this paper evaluates the performance of a SET-Memory based on NAND logic gates module considering the impact of non-ideal interconnects.