W-polycide dual-gate structure for sub-1/4 micron low-voltage CMOS technology

We describe a simple, low cost process, suitable for fabrication of low-voltage sub-1/4 micron CMOS devices, utilizing W-polycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200 nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P- and NMOS devices with connected gates are minimized (<30 mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both P- and NMOS devices have excellent I_on/I_off characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10 Ω/□