Optimization of high Q integrated inductors for multi-level metal CMOS

As the frequency standards for communication and other types of integrated circuits increase into the Gigahertz range, the use of integrated inductors becomes more and more feasible. Unfortunately, application of integrated inductors is hampered by a lack of design tools, and also useful models for how inductor properties vary with layout and how the inductor interacts with its environment. We discuss these issues and also analyze what we believe to be the optimal inductor layout for an unspecialized multi-layer metal submicron CMOS process. We conclude with a practical example of a 600 MHz communication circuit that can benefit from the availability of a good integrated inductor