MSB steps calibration algorithm for a pipelined ADC

A calibration algorithm that reduces differential nonlinearity errors in a pipelined ADC is described. N_C most significant bits are calibrated. The errors at the decision levels related to N_C bits are measured during a calibration cycle. The measurement is done by connecting analog input voltages, which are substantially the same as these decision levels, to the input of the ADC. Correction terms are calculated and stored into a RAM based on these errors. During the conversion, the correction terms are added to the raw output code of the ADC. The calibration does not slow down the ADC and only small modifications are needed to the logic of the pipeline stages that are to be calibrated to utilize this calibration algorithm. In addition to these modifications, three memories and some logic circuitry are needed