Evolution of conventional antilogarithmic approach and implementation in FPGA through VHDL

An antilog is the inverse function of a logarithm. Today, conventional use of the term “antilog” has been replaced in mathematics by the term “exponent”. The binary logarithm is often used in the field of computer science and information theory because it is closely connected to the binary numeral system, in the analysis of algorithms and Single-elimination tournaments etc. So an efficient system has to perform antilogarithm at higher speed, lower power consumption with minimal area requirement. In this paper calculation of antilogarithm of a number with any base is proposed through four different approaches where next approach is modified version of previous approach. Obviously modification is done in such a way that there is an improvement of area, power and delays at each subsequent stage. FPGA implementation of each method is done with which, following the simulation result, comparison of these 4 methods can be made. Xilinx 13.2 version is used for simulation. The VHDL approach for FPGA implementation is done in binary fix point with base 2. However it is possible to take any other base and proceed through same algorithm with some modification that will be explained later. Area, power, delay and error analysis is done. At the end possible optimization techniques are proposed for future modification.