Systematic design of high-linearity current-mode integrators for low-power continuous-time ΣΔ modulators

Author

Aboushady, Hassan ; Louërat, Marie-Minerve

Author_Institution

Lab. LIP6-ASIM, Paris VI Univ., France

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

963

Abstract

In this paper, the main sources of nonlinearity in current-mode continuous-time ΣΔ modulators are analyzed. The first integrator gain of the current-mode integrator is optimized to improve the linearity of the ΣΔ modulator. It is shown that by properly choosing the gain of the first integrator, harmonic distortion can be significantly reduced. A systematic design method for continuous-time ΣΔ modulators is presented. This method has been used to design two third order continuous-time ΣΔ modulators using 0.6 μm and 0.18 μm CMOS processes. Operating at a sampling frequency of 25.6 MHz, these modulators achieve 80 dB of SNDR for a 100 kHz input signal bandwidth

Keywords

CMOS integrated circuits; circuit CAD; continuous time systems; current-mode circuits; harmonic distortion; integrated circuit design; integrating circuits; sigma-delta modulation; signal sampling; ΣΔ modulator linearity; 0.18 micron; 0.6 micron; 100 kHz; 25.6 MHz; CMOS processes; SNDR; continuous-time ΣΔ modulators; current-mode continuous-time sigma-delta modulators; current-mode integrator; harmonic distortion; high-linearity current-mode integrators; input signal bandwidth; low-power continuous-time ΣΔ modulators; nonlinearity; optimized integrator gain; sampling frequency; systematic design; CMOS process; CMOS technology; Circuits; Equations; Harmonic analysis; Harmonic distortion; Linearity; Low voltage; Switches; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957633

Filename

957633