Reliability and yield: a joint defect-oriented approach

Author

Barsky, Roman ; Wagner, Israel A.

Author_Institution

Comput. Sci. Dept., Technion, Haifa, Israel

fYear

2004

Firstpage

2

Lastpage

10

Abstract

We present a model for computing the probability of a parametric failure due to a spot defect. The analysis is based on electromigration in conductors under unidirectional current stress. An analytical solution is given for simple layout and simulations for a more complicated case. Then we show that in some cases electromigration-dependent parametric defects can make a significant contribution to the total yield estimation.

Keywords

VLSI; circuit simulation; electromigration; failure analysis; integrated circuit interconnections; integrated circuit layout; integrated circuit metallisation; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; probability; IC reliability; IC yield; VLSI device reliability; conductor unidirectional current stress; electromigration; electromigration-dependent parametric defects; joint defect-oriented approach; layout; parametric failure probability model; simulations; total yield estimation; Computer science; Conductors; Electromigration; Frequency estimation; Production; Stress; Temperature; Very large scale integration; Wires; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2241-6

Type

conf

DOI

10.1109/DFTVS.2004.1347819

Filename

1347819