• DocumentCode
    1660319
  • Title

    VOQSW: a methodology to reduce HOL blocking in InfiniBand networks

  • Author

    Gómez, óM E. ; Flich, J. ; Robles, A. ; López, P. ; Duato, J.

  • Author_Institution
    Dept. of Comput. Eng., Univ. Politecnica de Valencia, Spain
  • fYear
    2003
  • Abstract
    InfiniBand is a new switch-based standard interconnect for communication between processor nodes and I/O devices as well as for interprocessor communication. InfiniBand architecture allows switches to support up to 15 virtual lanes per port for data traffic. To route packets through a given virtual lane (VL), packets are labeled with a certain service level (SL) at injection time, and SLtoVL mapping tables are used at each switch to determine the VL to be used. Many previous works in the literature have shown that separate virtual lanes are able to reduce the influence of the well-known head-of-line (HOL) blocking effect on network performance. However, using virtual lanes to form separate virtual networks is not enough to eliminate the HOL blocking problem. Alternative solutions such as Virtual Output Queuing (VOQ) are able to eliminate it at the expense of modifying the switch buffer organization. In this paper, we propose an effective strategy to implement the VOQ scheme in IBA switches by using virtual lanes. This strategy does not require to modify the switch architecture, simply SL to VL tables must be properly filled. Evaluation results show that our proposed VOQ scheme is able to outperform the results obtained with the virtual network approach using the same number of resources. Moreover, the methodology proposed to implement the VOQ scheme in IBA only requires a small number of resources in order to significantly improve network throughput.
  • Keywords
    computer networks; multiprocessor interconnection networks; performance evaluation; HOL blocking; InfiniBand networks; SL to VL mapping tables; VOQSW; head-of-line blocking effect; interprocessor communication; network performance; network throughput; switch buffer organization; switch-based standard interconnect; virtual lane; virtual output queuing; Communication standards; Communication switching; Computer aided manufacturing; Computer architecture; Intelligent networks; Isolation technology; Packet switching; Quality of service; Routing; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2003. Proceedings. International
  • ISSN
    1530-2075
  • Print_ISBN
    0-7695-1926-1
  • Type

    conf

  • DOI
    10.1109/IPDPS.2003.1213134
  • Filename
    1213134