Quantifying the improvement in energy savings for LTE eNodeB baseband subsystem with technology scaling and multi-core architectures

Recent wireless broadband cellular standards are aimed at making provisions for supporting very high data rate applications in limited available bandwidth. The most sophisticated as well as computationally complex subsystem of a transceiver of any such system is the baseband processing part of the system. A multi-core processor is typically needed to provide the required computational power for implementing the complex baseband processing subsystem such as that of LTE transceiver. The energy consumption in the baseband part of subsystem is a very significant component of the total energy expenditure of a cellular radio system, particularly when system employs MIMO and advanced VLSI state of art. This paper aims at reducing the energy consumption and also quantify the achievable energy savings by applying the recent trends in VLSI such as CMOS technology scaling and usage of new heterogeneous multi-core architectures specific to signal processing. To be able to explore and apply these energy efficient techniques, we have first estimated the energy consumption in LTE baseband functions then we have explored possible energy savings obtained from technology scaling and optimum heterogeneous combination of architectures for mapping baseband algorithms.