DocumentCode
1661115
Title
An efficient perfect algorithm for memory repair problems
Author
Lin, Hung-Yau ; Yeh, Fu-Min ; Chen, Ing-Yi ; Kuo, Sy-Yen
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2004
Firstpage
306
Lastpage
313
Abstract
Memory repair by using spare rows/columns to replace faulty rows/columns has been proved to be NP-complete. Traditional perfect algorithms are comparison-based exhaustive search algorithms and are not efficient enough for complex problems. To overcome the deficiency of performance, a new algorithm has been devised and presented in this paper. The algorithm transforms a memory repair problem into Boolean function operations. By using BDD (binary decision diagram) to manipulate Boolean functions, a repair function which encodes all repair solutions of a memory repair problem can be constructed. The optimal solution, if it exists, can be found efficiently by traversing the BDD of a repair function only once. The algorithm is very efficient due to the fact that BDD can remove redundant nodes, combine isomorphic subgraphs together, and have very compact representations of Boolean functions if a good variable ordering is chosen. The remarkable performance of the algorithm can be demonstrated by experimental results. Because a memory repair problem can be modeled as a bipartite graph, the algorithm may be useful for researchers in other fields such as graph theory.
Keywords
Boolean functions; VLSI; binary decision diagrams; graph theory; integrated circuit design; integrated memory circuits; logic design; maintenance engineering; problem solving; redundancy; BDD; Boolean function operations; NP-complete problem; binary decision diagram; bipartite graph model; comparison-based exhaustive search algorithms; efficient perfect algorithm; encoded repair solutions; faulty columns; faulty rows; graph theory; isomorphic subgraphs; memory repair problems; redundant nodes; repair function BDD; spare columns; spare rows; variable ordering; Approximation algorithms; Binary decision diagrams; Boolean functions; Computer science; Data structures; Heuristic algorithms; Random access memory; Read-write memory; Semiconductor device manufacture; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2241-6
Type
conf
DOI
10.1109/DFTVS.2004.1347853
Filename
1347853
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