• DocumentCode
    1661215
  • Title

    A universal testability strategy for multi-chip modules based on BIST and boundary-scan

  • Author

    Zorian, Yervant

  • Author_Institution
    AT&T Bell Lab., Princeton, NJ, USA
  • fYear
    1992
  • Firstpage
    59
  • Lastpage
    66
  • Abstract
    A testability strategy that can be implemented mainly by incorporating built-in self-test (BIST) and boundary scan during the chip design cycle is presented. On the basis of these, the testing and diagnosis procedures needed to meet the quality requirements of multichip module (MCM) manufacturing, and hence reaching acceptable MCM assembly yields is demonstrated. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate, or attachment technologies adopted to build the MCM
  • Keywords
    boundary scan testing; built-in self test; multichip modules; BIST; assembly yields; boundary-scan; chip design cycle; diagnosis procedures; multi-chip modules; quality requirements; universal testability strategy; Assembly; Automatic testing; Built-in self-test; CMOS technology; Costs; Manufacturing; Military computing; Packaging; Silicon; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-3110-4
  • Type

    conf

  • DOI
    10.1109/ICCD.1992.276206
  • Filename
    276206