A composite data Prefetcher framework for multilevel caches

The increasing difference between the Processor speed and the DRAM performance have led to the assertive need to hide memory latency and reduce memory access time. It is noticed that the Processor remains stalled on memory references. Data Prefetching is a technique that fetches that next instruction´s data parallel to the current instruction execution in a typical Processor-Cache-DRAM system. A Prefetcher anticipates a cache miss that might take place in the next instruction and fetches the data before the actual memory reference. The goal of prefetching is to reduce as many cache misses as possible. In this paper we present a detailed summary of the different prefetching techniques, and implement a composite prefetcher prototype that employs the techniques of Sequential, Stride and Distance Prefetching.