DocumentCode
1661431
Title
Alpha architecture: Hardware implementation and software programming implications
Author
Meyer, Derrick
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1992
Firstpage
4
Lastpage
5
Abstract
A description is given of Alpha, a 64-bit RISC architecture designed with emphasis on clock speed, multiple instruction issues and multiple processors. The author discusses byte manipulation, arithmetic traps, shared memory, the Privileged Architecture Library (PALcode), and Alpha´s attractiveness for compiling a large variety of programming languages
Keywords
reduced instruction set computing; 64 bit; 64-bit RISC architecture; Alpha architecture; Hardware implementation; PALcode; Privileged Architecture Library; arithmetic traps; byte manipulation; clock speed; multiple instruction issues; multiple processors; shared memory; software programming; Arithmetic; Buildings; Computer architecture; Delay; Hardware; Logic; Pipeline processing; Read-write memory; Reduced instruction set computing; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-3110-4
Type
conf
DOI
10.1109/ICCD.1992.276216
Filename
276216
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