VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

Author

Xu, Donglai ; Bentley, John

Author_Institution

Sch. of Sci. & Technol., Teeside Univ., Middlesbrough, UK

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

217

Abstract

In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; field programmable gate arrays; image matching; image processing equipment; motion estimation; parallel architectures; video coding; FPGA addressing circuit; H.261 standard; VLSI tree processor; VLSI-based parallel architecture; block-matching motion estimation; improved three-step search motion estimation algorithm; low bit-rate video coding; Circuits; Computer architecture; Costs; Field programmable gate arrays; Motion estimation; Parallel architectures; Pipelines; Silicon; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957719

Filename

957719