• DocumentCode
    1662842
  • Title

    Diagnosis of hold time defects

  • Author

    Zhiyuan Wang ; Marek-Sadowska, M. ; Kun-Han Tsai ; Rajski, J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
  • fYear
    2004
  • Firstpage
    192
  • Lastpage
    199
  • Abstract
    In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this work, we analyze failures caused by the hold-time-violations. We investigate the feasibility of using circuit-timing information to guide the hold-time-fault diagnosis. We propose a novel and efficient diagnostic approach based on timing window propagation. For each identified candidate, our method locates the source of the hold-time violation and determines the most probable defect size. Experimental results indicate that the new method diagnoses hold-time related defects with very good resolution.
  • Keywords
    failure analysis; fault diagnosis; timing circuits; circuit timing information; hold time defect diagnosis; hold time fault diagnosis; hold time violations; timing window propagation; Circuits; Clocks; Computer errors; Crosstalk; Delay effects; Design engineering; Flip-flops; Jitter; Propagation delay; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-2231-9
  • Type

    conf

  • DOI
    10.1109/ICCD.2004.1347921
  • Filename
    1347921