Analysis of multi-bit flip flop low power methodology to reduce area and power in physical synthesis and clock tree synthesis in 90nm CMOS technology

Power and Area has become a burning issue in modern VLSI design. Power has become a bottleneck in digital circuit in ultra-deep sub-micron design. Clock power is one of the major power sources. As design size reduces Area also become a major concern. The Multi bit Flip Flop is one of the methodologies to reduce power and area. By using MBFF methodology in physical design flow, we can also reduce the global congestion as wire length reduces significantly. For a given design, we can reduce its power, area and wire length through merging of flip-flops without affecting functionality of design and achieve better quality results. In this paper, we will review multi bit flip flops concepts, library syntax for MBFF and analytical study of design´s results with MBFF and without MBFF at Physical Synthesis and clock tree synthesis on 90nm technology.