Distributed arithmetic radix-2 butterflies for FPGA

Author

Sansaloni, T. ; Perez-Pascual, A. ; Valls, J.

Author_Institution

Dpto. Ing. Electronica, Univ. Politecnica de Valencia, Spain

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

521

Abstract

This paper systematizes the design of radix-2 DIF butterflies for large FFTs based on distributed arithmetic. The butterflies are suitable for FFTs up to 4096 points and have been efficiently mapped on FPGA. Two improvements have been proposed with respect the previously published structures. First, the use of 5-input LUTs allows codifying higher number of angles per stage and does not reduce the throughput. Second, minimum area butterflies are obtained by combining the three methods explained in the paper. In such a case, the performance is increased: the area and the latency are reduced and the throughput is increased

Keywords

distributed arithmetic; fast Fourier transforms; field programmable gate arrays; table lookup; 5-input LUTs; FPGA; angle codifying; area; complex-number multiplications; distributed arithmetic radix-2 butterflies; large FFTs; latency; look-up tables; minimum area butterflies; radix-2 DIF butterflies; throughput; twiddle factors; Arithmetic; Delay; Digital signal processing; Fast Fourier transforms; Field programmable gate arrays; Flexible printed circuits; Mobile communication; Table lookup; Throughput; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957793

Filename

957793