A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy

Decreasing operating margins due to random variations is a key issue for voltage scaling in SRAM technology. It is particularly severe for half-select disturb because both write and read occur at the same row. While a wordline (WL) voltage assist technique [1] does not improve half-select disturbs, a negative bitline (BL) scheme [2] or asymmetric pass gate (PG) transistor with higher V_TH during read [3] can be effective for mitigating half-select disturbs. While these techniques can increase operating margins, they cannot specifically target cells to correct for random variations.