• DocumentCode
    1665399
  • Title

    Power efficiency of application-dependent self-configuring pipeline depth in DSP microprocessors

  • Author

    Olivieri, Mauro ; Raspa, Marco

  • Author_Institution
    La Sapienza Univ., Rome, Italy
  • fYear
    2003
  • Abstract
    We illustrate the results of a simulation-based analysis of "self-configuring" pipeline depth in DSP computations, focusing on the effects on power efficiency. We use three different metrics for power efficiency: mips/watts, mips2/watts, and watts under an absolute performance constraint. Our results, based on a set of commercial DSP benchmarks, show that an application-dependent self-configuring pipeline depth significantly affects power efficiency.
  • Keywords
    digital signal processing chips; logic simulation; DSP microprocessors; application-dependent self-configuring pipeline depth; performance constraint; simulation-based analysis; Analytical models; Application software; Computational modeling; Computer architecture; Delay; Digital signal processing; Energy consumption; Energy measurement; Microprocessors; Pipelines;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2003. Proceedings. International
  • ISSN
    1530-2075
  • Print_ISBN
    0-7695-1926-1
  • Type

    conf

  • DOI
    10.1109/IPDPS.2003.1213342
  • Filename
    1213342
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1665399