Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC´s

Author

Ker, Ming-Dou ; Chung-Yu Wu ; Cheng, Tao ; Chang, Hun-Hsien ; Wu, Michael J N ; Yu, T.-L.

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1995

Firstpage

193

Lastpage

195

Abstract

A novel square-type layout style is proposed to efficiently implement CMOS output buffer with larger W/L ratio into a smaller silicon layout area than that of conventional finger-type layout style. Using this proposed layout style, the driving capability of CMOS output buffer in low-voltage submicron CMOS IC´s can be effectively improved without increasing the layout area

Keywords

CMOS integrated circuits; buffer circuits; integrated circuit layout; CMOS output buffer; IC layout style; LV submicron CMOS ICs; driving capability improvement; square-type layout style; CMOS integrated circuits; CMOS process; CMOS technology; Current density; Electronic mail; Industrial electronics; Integrated circuit layout; Laboratories; MOS devices; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1995 4th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-3062-5

Type

conf

DOI

10.1109/ICSICT.1995.499780

Filename

499780

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1667129