Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS

Flip-flops (FFs) are key building blocks in the design of high-speed energy-efficient microprocessors, as their data-to-output delay (D-Q) and power dissipation strongly affect the processor´s clock period and overall power. From pre vious analyses, the Transmission-Gate Pulsed Latch (TGPL) proved to be the most energy-efficient FF in a large portion of the design space, ranging from high speed (minimizing ED´ products with j>;1) to minimum ED product designs, while simple Master-Slave FFs (TGFF and ACFF ) are the most energy-efficient in the low-power E-D space region. TGPL also has the lowest D Q delay along with STFF. However, the latter has considerably worse energy efficiency, hence, the TGPL is the best reference for a comparison. In this work, two new FFs are introduced, the Conditional Push-Pull Pulsed Latch (CP3L), and a version with a Shareable (CSP3L) Pulse Generator (PG). The adoption of a fast push-pull second stage, which requires a conditional PG, enables 50-to-100% delay improvements compared to TGPL, and absolute D-Q up to 0.7FO4. CP3L and CSP3L also exhibit superior energy efficiency to TGPL in terms of minimum ED3 and ED products. A test chip is fabricated in 65nm CMOS technology (VDD=1V) to measure delay and energy consumption of CP3L, CSP3L and TGPL in minimum ED and ED3 sizings. Different loadings are used in the mini mum ED (16χ) and the minimum ED3 (64χ) cases.