10–40 Gb/s I/O design for data communications

The importance of I/O data rates beyond 10Gb/s is growing rapidly. Supporting these data rates introduces new challenges beyond those faced at lower data rates. The objective of this forum is to present both electrical and optical I/O approaches to meeting these challenges at the architecture and circuit levels. This forum commences with two talks offering an overview of circuits and systems issues in CMOS technology. They are followed by two presentations focusing on the challenges of 20Gb/s+ over electrical backplanes and very lossy electrical channels. The next talk compares conventional analog equalization versus digital (data converter based) approaches from a system perspective. The final two talks focus on optical solutions, highlighting the relative strengths and weaknesses of electrical and optical approaches. The forum concludes with a panel discussion providing the opportunity for participants to give feedback and ask questions. The forum is aimed at circuit designers and engineers working on high-speed wireline transceivers.