VLSI video codec using programmable DSP

Author

Tajiri, Takahiro ; Suzuki, Yutaka ; Yoshimura, Hiroshi

Author_Institution

NTT Human Interface Labs., Kanagawa, Japan

fYear

1992

Firstpage

479

Abstract

A video codec based on CCITT´s standardized p×64 video coding algorithm and communication protocol has been developed for ISDN H0 rate transmission. The codec is fabricated on two 280-mm×280-mm boards and is composed of new DSPs, four kinds of NTSC-CIF (National Television Committee-Common Intermediate Format) mutual conversion LSIs, a transmission codec LSI, and an AD/DA (analog-to-digital/digital-to-analog) hybrid IC. The codec codes and decodes full CIF signs at a rate of 15 frames/s and communicates at an ISDN 384-kb/s rate. Application programs for the codec, such as picture reconstruction capability driven by DSPs in the coder or decoder, can be performed by using residual DSP processing power without the need for any hardware addition

Keywords

VLSI; codecs; digital signal processing chips; video equipment; 384 kbit/s; CCITT; ISDN H0 rate transmission; NTSC-CIF; VLSI; application programs; picture reconstruction; programmable DSP; transmission codec LSI; video codec; video coding algorithm; Analog integrated circuits; Decoding; Digital signal processing; ISDN; Large scale integration; Protocols; TV; Very large scale integration; Video codecs; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1992. Conference Record., GLOBECOM '92. Communication for Global Users., IEEE

Conference_Location

Orlando, FL

Print_ISBN

0-7803-0608-2

Type

conf

DOI

10.1109/GLOCOM.1992.276549

Filename

276549