A non-linearity self-calibration technique for delay-locked loop delay-lines

An on-chip non-linearity self-calibration of a CMOS all-digital shunt capacitor delay-line is achieved by first measuring the non-linearity of each delay-cell by means of a statistical test and then correcting the individual cell delay mismatch according to the test results. An iterative calibration algorithm has been developed and a fully digital circuit efficiently implementing the calibration procedure has been designed. The same digital controller is used to sequentially calibrate each delay-cell, so that the occupied silicon area is minimized. Simulation results show the feasibility of the technique and a substantial reduction of the maximum non-linearity down to values close to 1%.