On-chip timing slack monitoring

Author

Rebaud, B. ; Belleville, M. ; Beigné, E. ; Robert, M. ; Maurine, P. ; Azemard, N.

Author_Institution

CEA, MINATEC, Grenoble, France

fYear

2009

Firstpage

89

Lastpage

94

Abstract

PVT monitors are mandatory to use tunable knobs designed to compensate the variability effects. This paper describes a new on-chip monitoring system, allowing failure anticipation in real-time, in looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of special structures situated near the flip-flops, coupled with a specific detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area fine-grain system, easily insertable in a standard CAD flow.

Keywords

flip-flops; integrated circuit measurement; integrated circuit reliability; integrated circuit testing; timing circuits; PVT monitors; clock-tree; flip-flops; low area fine-grain system; low power fine-grain system; on-chip monitoring system; on-chip timing slack monitoring; process voltage temperature; size 45 nm; standard CAD flow; window generator; Clocks; Image edge detection; Latches; Monitoring; Power demand; Sensors; Timing; Variability; monitor; process compensation; timing slack;

fLanguage

English

Publisher

ieee

Conference_Titel

Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on

Conference_Location

Florianopolis

Print_ISBN

978-1-4577-0237-2

Type

conf

DOI

10.1109/VLSISOC.2009.6041336

Filename

6041336