Crosstalk fault tolerant NoC - Design and evaluation

Networks-on-chip (NoCs) interconnection infrastructure was proposed to maximize the integration level of multiple processing elements in the same chip. New applications require a high performance communication infrastructure with low data latency. The innovations on integrated circuit fabrics is continuously reducing components size, which increases the logic density of systems-on-chip (SoC), but also affect the reliability of these components. This work presents an implementation of an error recovery technique for networks-on-chip with the objective to protect network links against crosstalk effects, minimizing the latency of error recovery, with minimal area overhead. Results of the proposed technique are illustrated by simulating the network with crosstalk fault simulation, measuring latency and area overhead.