DocumentCode
1670171
Title
A study on WK-recursive topology using gpNoCsim++ simulator and comparison to Other topologies
Author
Jamali, Mohammad Ali Jabraeil ; Bahrbegi, Hadi ; Ahrabi, Amir Azimi Alasti ; Bahrbegi, Mehdi
Author_Institution
Islamic Azad Univ., Shabestar, Iran
fYear
2009
Firstpage
181
Lastpage
184
Abstract
Network-on-Chip (NoC) was first invented to tackle with the problem of communication in System-on-Chip (SoC). SoC uses a shared bus to communicate between components. All architectures based on a shared bus have some inherent problems as limited scalability and shared bus becoming a bottleneck. NoC offers a scalable architecture and capability of complex topological design. The architecture is inspired from computer networks. Although it is similar to computer networks from routing, switching and topology point of view but consumption of energy and space is too important for NoC. This article studies WK-recursive topology for NoC. The topology is simulated with gnNoCSim++ and performance metrics is compared to Fat Tree, Extended-Butterfly Fat Tree Interconnection (EFTI), Mesh, Torus and Octagon. The comparison shows strengths and weaknesses of WK-recursive.
Keywords
integrated circuit interconnections; network routing; network topology; network-on-chip; WK-recursive topology; complex topological design; computer networks; extended-butterfly fat tree interconnection; gpNoCsim++ simulator; network-on-chip; routing; scalable architecture; system-on-chip; Computer architecture; IP networks; Measurement; Network topology; Switches; Throughput; Topology; Network-on-Chip; Simulation; Topology; WK-recursive; gpNoCSim++;
fLanguage
English
Publisher
ieee
Conference_Titel
Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on
Conference_Location
Florianopolis
Print_ISBN
978-1-4577-0237-2
Type
conf
DOI
10.1109/VLSISOC.2009.6041351
Filename
6041351
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