Distributed Arithmetic for FIR Filter Design on FPGA

This paper presents a distributed arithmetic (DA) for highly efficient multiplier-less FIR filter designed on FPGA. First, the theory of the distributed arithmetic is described. Furthermore, a modification of the DA based on the look up table (LUT) and filter structure to implement the high-order filter hardware-efficient on FPGA is introduced. The proposed filter has been designed and synthesized with ISE 7.1, and implemented with a 4VLX40FF668 FPGA device. Our results show that the proposed DA architecture can implement FIR filters with the smaller resource usage and similar speed in comparison to the previous DA architecture.