• DocumentCode
    167215
  • Title

    Taking Advantage of Hybrid Systems for Sparse Direct Solvers via Task-Based Runtimes

  • Author

    Lacoste, Xavier ; Faverge, Mathieu ; Ramet, Pierre ; Thibault, Samuel ; Bosilca, George

  • Author_Institution
    INRIA, Univ. of Bordeaux, Talence, France
  • fYear
    2014
  • fDate
    19-23 May 2014
  • Firstpage
    29
  • Lastpage
    38
  • Abstract
    The ongoing hardware evolution exhibits an escalation in the number, as well as in the heterogeneity, of computing resources. The pressure to maintain reasonable levels of performance and portability forces application developers to leave the traditional programming paradigms and explore alternative solutions. PaStiX is a parallel sparse direct solver, based on a dynamic scheduler for modern hierarchical manycore architectures. In this paper, we study the benefits and limits of replacing the highly specialized internal scheduler of the PaStiX solver with two generic runtime systems: PaRSEC and StarPU. The tasks graph of the factorization step is made available to the two runtimes, providing them the opportunity to process and optimize its traversal in order to maximize the algorithm efficiency for the targeted hardware platform. A comparative study of the performance of the PaStiX solver on top of its native internal scheduler, PaRSEC, and StarPU frameworks, on different execution environments, is performed. The analysis highlights that these generic task-based runtimes achieve comparable results to the application-optimized embedded scheduler on homogeneous platforms. Furthermore, they are able to significantly speed up the solver on heterogeneous environments by taking advantage of the accelerators while hiding the complexity of their efficient manipulation from the programmer.
  • Keywords
    embedded systems; multiprocessing systems; parallel programming; scheduling; PaRSEC system; PaStiX parallel sparse direct solver; StarPU system; application-optimized embedded scheduler; dynamic scheduler; hierarchical manycore architecture; homogeneous platform; programming paradigm; task-based runtime; Computer architecture; Graphics processing units; Linear algebra; Processor scheduling; Programming; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International
  • Conference_Location
    Phoenix, AZ
  • Print_ISBN
    978-1-4799-4117-9
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2014.9
  • Filename
    6969368