A single-chip transceiver for 802.11a and Hiperlan2 wireless LANs

Author

Pipilos, S. ; Metaxakis, Emmanuel ; Tzimas, Apostolos ; Vlassis, Spyros ; Sgourenas, Savvas ; Tsividis, Yannis ; Varelas, Theodore

Author_Institution

Theta Microelectron., Athens, Greece

fYear

2003

Firstpage

33

Lastpage

36

Abstract

A fully integrated transceiver for 802.11a and Hiperlan2 wireless local area network applications is described. This single-chip transceiver employs direct conversion with on-chip channel-select filters and DC offset cancellation servo circuitry, as well as correction loops for maintaining accurate I/Q balancing and transmitter power control. The transceiver exceeds both WLAN standard requirements for the 54 Mbps mode, demonstrating a receiver sensitivity of -75 dBm for this mode. A highly flexible interface allows a variety of baseband processors to interface with this chip.

Keywords

IEEE standards; integrated circuit design; telecommunication standards; transceivers; wireless LAN; 5 to 6 GHz; 54 Mbit/s; DC offset cancellation servo circuitry; Hiperlan2 wireless local area networks; I/Q balancing correction loops; IEEE 802.11a standard; WLAN; baseband processor interfaces; direct conversion single-chip transceivers; on-chip channel-select filters; receiver sensitivity; transmitter power control; wireless LAN; Filters; Local area networks; OFDM; Power control; Radio transmitters; Synthesizers; Transceivers; Voltage control; Voltage-controlled oscillators; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE

ISSN

1529-2517

Print_ISBN

0-7803-7694-3

Type

conf

DOI

10.1109/RFIC.2003.1213887

Filename

1213887