• DocumentCode
    1672925
  • Title

    A self-biased PLL with current-mode filter for clock generation

  • Author

    Yan, Gang ; Ren, Chenxiao ; Guo, Zhendong ; Ouyang, Qing ; Chang, Zhongyuan

  • Author_Institution
    IDT-Newave Technol., Shanghai, China
  • fYear
    2005
  • Firstpage
    420
  • Abstract
    A self-biased PLL with current mode filter is designed to achieve a bandwidth that scales with reference clock and is independent of PVT and multiplication factor. It provides wide tuning range with a simple robust structure. The 0.2mm2 chip is fabricated in 0.35 μm CMOS. Running at 800MHz, the phase jitter is 72.7pspp and the power consumption is 20mW.
  • Keywords
    CMOS integrated circuits; circuit tuning; clocks; current-mode circuits; phase locked loops; timing jitter; 0.35 micron; 20 mW; 800 MHz; CMOS; clock generation; current-mode filter; phase jitter; reference clock; self-biased PLL; tuning range; 1f noise; Bandwidth; Charge pumps; Clocks; Filters; Frequency; Jitter; Phase locked loops; Temperature; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494048
  • Filename
    1494048
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1672925