DocumentCode
1673360
Title
A 322MHz random-cycle embedded DRAM with high-accuracy sensing and tuning
Author
Iida, M. ; Kuroda, N. ; Otsuka, H. ; Hirose, M. ; Yamasaki, Y. ; Ohta, K. ; Shimakawa, K. ; Nakabayashi, T. ; Yamauchi, H. ; Sano, T. ; Gyohten, T. ; Maruta, M. ; Yamazaki, A. ; Morishita, F. ; Dosaka, K. ; Takeuchi, M. ; Arimoto, K.
Author_Institution
Matsushita, Kyoto, Japan
fYear
2005
Firstpage
460
Abstract
An embedded DRAM macro in a logic compatible 90nm CMOS process is designed with low-noise core architecture and high-accuracy post-fabrication tuning. With a 5fF/cell capacitance, a 61% improvement of sensing accuracy enables 322MHz random-cycle operation and reduces data retention power to 60 μW.
Keywords
CMOS memory circuits; DRAM chips; circuit tuning; embedded systems; 322 MHz; 5 fF; 60 muW; 90 nm; CMOS process; data retention power; high-accuracy sensing; low-noise core architecture; post-fabrication tuning; random-cycle embedded DRAM; Capacitors; Circuit noise; Costs; Coupling circuits; Delay; Metal-insulator structures; Noise cancellation; Noise reduction; Random access memory; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1494068
Filename
1494068
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