Realistic dynamic timing verification for complex mixed signal hard macro´s using UVM

The paper addresses an attempt to perform dynamic timing simulations of complex mixed signal IP´s. The targeted IP is a memory and uses its behavioural model; the idea spans from checking the presence of IO Path delays and timing checks viz. setup, hold, recovery, removal, width etc, and validating the impact on the IP behaviour. The methodology is developed and validated on UVM semantics; the eco-system is customized to incorporate an ad-hoc timing algorithm. This approach has proven to be flexible and accurate in validating the timing behaviour of the memory models which boosted up the functional coverage. It has also helped in catching strategic and systemic bugs that would have not been caught otherwise. This approach though tested on memories, is applicable to any AMS IP´s having timing checks.