• DocumentCode
    1673532
  • Title

    A 256MB synchronous-burst DDR SRAM with hierarchical bit-line architecture for mobile applications

  • Author

    Suh, Y.H. ; Nam, H.Y. ; Kang, S.B. ; Choi, B.G. ; Mo, H.S. ; Han, G.H. ; Shin, H.K. ; Jung, W.R. ; Lim, H. ; Kwak, C.K. ; Byun, H.-G.

  • Author_Institution
    Samsung, Hwasung, South Korea
  • fYear
    2005
  • Firstpage
    476
  • Abstract
    RZ current switches are added to a current steering DAC for high-frequency wideband applications to achieve 800MHz bandwidth at 1st and 2nd Nyquist band without the need for a reverse sinc equalization filter. Implemented in a GaAs HBT process with 4.5 μm2 minimum emitter area, the DAC dissipates 1.2W at -5V with a 1.6GHz clock and 0dBm typical output power.
  • Keywords
    SRAM chips; bipolar integrated circuits; gallium arsenide; heterojunction bipolar transistors; mobile computing; switches; -5 V; 1.2 W; 1.6 GHz; 256 MB; 800 MHz; GaAs; GaAs HBT process; Nyquist band; RZ current switches; current steering DAC; hierarchical bit-line architecture; high-frequency wideband applications; mobile applications; synchronous-burst DDR SRAM; Decoding; Driver circuits; Joining processes; Parasitic capacitance; Random access memory; Silicon; Stacking; Switching circuits; Thin film transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494076
  • Filename
    1494076
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1673532