• DocumentCode
    1673738
  • Title

    A 4th-order 86dB CT ΔΣ ADC with two amplifiers in 90nm CMOS

  • Author

    Das, Abhijit ; Hezar, Rahmi ; Byrd, Russell ; Gomez, Gabriel ; Haroun, Baher

  • Author_Institution
    Texas Instrum. Inc., Dallas, TX, USA
  • fYear
    2005
  • Firstpage
    496
  • Abstract
    A fourth-order 1b CT ΔΣ converter using a two-amplifier loop and a 267MHz sampling frequency is implemented in 90nm CMOS. A double-loop architecture couples passive poles with a reduced number of active blocks to improve area and power while achieving 86dB peak SNR over a 600kHz band.
  • Keywords
    CMOS integrated circuits; amplifiers; delta-sigma modulation; signal sampling; 267 MHz; 600 kHz; 90 nm; CMOS; double-loop architecture; fourth-order CT ΔΣ converter; passive poles; reduced active blocks; sampling frequency; two-amplifier loop; 1f noise; Bandwidth; Capacitors; Energy consumption; Jitter; Low voltage; Noise reduction; Passive filters; Poles and zeros; Sampling methods;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494086
  • Filename
    1494086
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1673738