DocumentCode
1673870
Title
Processor configuration for real-time SAR image generation
Author
Einstein, Thomas H.
Author_Institution
Mercury Comput. Syst. Inc., Chelmsford, MA, USA
fYear
1998
Firstpage
68
Lastpage
73
Abstract
This paper describes how to configure a multicomputer for real-time SAR image generation so as to minimize either the total number of processors or the amount of data buffer memory required. The total number of processors is minimized by arranging the processors in a pipeline of parallel processor clusters, with double-buffering at the input and output of each cluster. In contrast, the total memory requirement is minimized by implementing the application on a round-robin arrangement of identical processor modules, each module consisting of a single cluster of parallel processors. Depending upon the incoming data rate to be processed, the memory requirement of this minimum-memory configuration may be as little as one-eighth that of the minimum-processor pipeline configuration, at the cost of between 25 and 70% more processors
Keywords
buffer storage; parallel architectures; pipeline processing; radar computing; radar imaging; real-time systems; synthetic aperture radar; data buffer memory; data rate; double-buffering; memory requirement minimization; minimum-memory configuration; minimum-processor pipeline configuration; multicomputer; parallel processor cluster; pipeline processor cluster; processor modules; real-time SAR image generation; round-robin arrangement; Computer buffers; Cooling; Costs; Data buses; Data communication; Energy consumption; Image generation; Multiprocessor interconnection networks; Pipelines; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Radar Conference, 1998. RADARCON 98. Proceedings of the 1998 IEEE
Conference_Location
Dallas, TX
Print_ISBN
0-7803-4492-8
Type
conf
DOI
10.1109/NRC.1998.677979
Filename
677979
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