Area compact 5T portless SRAM cell for high density cache in 65nm CMOS

High performance SOC contains considerable amount of SRAM memory occupying more than 60% of total SOC area. In CMOS process scaling down of feature size enables higher density and lower cost but high density array has significant impact on manufacturing yield and performance parameters of conventional 6T SRAM cell. In this paper we have presented an alternate area compact 5 transistor portless SRAM cell in 65nm CMOS technology. Various performance and reliability issues of 5T cell have been addressed. This 5T cell has shown to have 20-30% area reduction without any significant performance degradation as compared to the conventional 6T SRAM cell.