Modified low power scan based technique

The testing power is the biggest concern in modern VLSI chip testing as the testing power is very greater than the functional power which affects the reliability of the chip. In this paper low test power architecture is proposed which loads the pattern in one scan chain serially and the rest scan chains are loaded parallel by the serial scan chain one after the other. The proposed technique is very effective in test power reduction as the serial shifting happens only in one scan chain which reduces the switching activity in other scan chains. From the experiments conducted on ISCAS89 benchmark circuits, the proposed low test power architecture reduces the test power by 65% with additional test cycles.