An all digital delay lock loop architecture for high precision timing generator

Remote sensing satellites use Charge Coupled Detectors (CCD) to achieve lower noise and higher dynamic range. Operation of a CCD requires high precision clocks/sequences. Generally it is achieved by using Phase Locked loop (PLL) or Delay Lock Loop (DLL). DLL are preferred for their low noise. An All Digital Delay Lock Loop (ADDLL) is designed to be used in the timing generation core. It is implemented using RTL design flow. This paper discusses design and implementation of an All Digital Delay lock loop suitable for implementation using RTL design methodology. It shows detailed blocks and implementation. It also discusses the challenges faced and their solutions in using RTL design for implementing this DLL. The resolution achieved was 620 ps in 180nm technology with phase error of 232 ps.